Memory circuits typically include sense amplifiers for amplifying output data read from selected memory cells, and output latches for retaining the amplified output data while other components of the memory circuit are shut down between read and write operations to reduce power consumption. The output latches must not operate until the amplified output data has stabilized at the correct output value. Otherwise, incorrect output data may be retained by the output latches and passed to circuits connected to the memory circuits.
To ensure that output latches retain correct output data, the output latches may be triggered by a signal which is timed so as to ensure that the amplified output data has already stabilized at the correct output value. Such a signal may be derived from the signal used to initiate the read operation by passing that signal through a delay element designed to simulate the delay between initiation of a read operation and stabilization of correct amplified output data. Such delay elements often comprise a series of inverters and delay capacitors.
Unfortunately variations in processes used to manufacture a memory circuit may have different effects on components used to construct delay elements and on other components of the memory circuit so that the delay provided by delay elements may not match the delay due to other components of the memory circuit. To ensure correct operation of the memory circuit, it is therefore necessary to build some timing margin into the simulated delay, and this timing margin increases the access and cycle times of the memory circuit.
The required timing margin can be reduced somewhat by constructing the delay element from components which are similar or identical to the components of the memory circuit which contribute to the delay between initiation of a read operation and stabilization of correct amplified output data. Variations in manufacturing process should then have more similar effects on the delay provided by the delay element and the delay provided by other components of the memory circuit. However, in large memory circuits, the components making up the delay element may be thousands of microns away from the components which contribute to the delay between initiation of a read operation and stabilization of correct amplified output data. Because processing conditions vary somewhat across the surface of large substrates, the simulated delay may still differ from the delay provided by other components of the memory circuit. Consequently, some timing margin is still required, and this remaining timing margin increases the access and cycle times of the memory circuit.
Alternatively, the output latches may be configured so that they cannot operate until valid amplified output data is supplied. For example, RS output latches may have Set and Reset inputs connected respectively to positive and negative outputs of corresponding sense amplifiers, so that the output latches will not operate until a valid "1" is applied to one of the Set or Reset inputs. Unfortunately, the sense amplifier input signal may develop slowly so that there is a considerable delay before a valid "1" is applied to an input of the output latch, and this increases memory access and cycle time.